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» Dynamic Simultaneous Multithreaded Architecture
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ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
15 years 8 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
104
Voted
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
15 years 8 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
140
Voted
EAGC
2003
Springer
15 years 7 months ago
Automatic Services Discovery, Monitoring and Visualization of Grid Environments: The MapCenter Approach
The complexity of Grid environments is growing as more projects and applications appear in this quick-evolving domain. Widespread applications are distributed over thousands of com...
Franck Bonnassieux, Robert Harakaly, Pascale Prime...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 6 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
IPPS
2006
IEEE
15 years 8 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner