239 search results - page 42 / 48 » Dynamic Simultaneous Multithreaded Architecture |
116
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DAC
1998
ACM
15 years 5 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
132
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DAC
2003
ACM
16 years 2 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
134
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VLSID
2003
IEEE
16 years 2 months ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
108
Voted
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
95
Voted
ISCC
2008
IEEE
15 years 8 months ago
2008
IEEE
In this paper, a novel solution to dynamically control the resources of a WiMAX system is proposed. The presented solution is aligned with the NGN trends, as well as with the WiMA...