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180
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DAC
2003
ACM
16 years 4 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou
129
Voted
EGH
2004
Springer
15 years 9 months ago
A flexible simulation framework for graphics architectures
In this paper we describe a multipurpose tool for analysis of the performance characteristics of computer graphics hardware and software. We are developing Qsilver, a highly conï¬...
Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron
137
Voted
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 9 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
153
Voted
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 8 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
123
Voted
DAC
2000
ACM
16 years 4 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...