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126
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CODES
2005
IEEE
15 years 9 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
141
Voted
CASES
2005
ACM
15 years 5 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
173
Voted
CF
2004
ACM
15 years 9 months ago
An architectural framework and a middleware for cooperating smart components
In a future networked physical world, a myriad of smart sensors and actuators assess and control aspects of their environments and autonomously act in response to it. Examples ran...
Antonio Casimiro, Jörg Kaiser, Paulo Ver&iacu...
185
Voted
UIST
1993
ACM
15 years 7 months ago
VB2: An Architecture for Interaction in Synthetic Worlds
This paper describes the VB2 architecture for the construction of three-dimensional interactive applications. The system's state and behavior are uniformly represented as a n...
Enrico Gobbetti, Jean-Francis Balaguer, Daniel Tha...
148
Voted
TPDS
2010
174views more  TPDS 2010»
15 years 2 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra