989 search results - page 100 / 198 » Dynamic Symmetry Reduction |
142
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ISVLSI
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
137
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VTS
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
121
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ICCAD
1998
IEEE
15 years 8 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
126
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WCET
2008
15 years 5 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...
CORR
2010
Springer
15 years 4 months ago
2010
Springer
Abstract. Ariola and Felleisen's call-by-need -calculus replaces a variable occurrence with its value at the last possible moment. To support this gradual notion of substituti...