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HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
HIPEAC
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...