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151
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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 8 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
138
Voted
SENSYS
2003
ACM
15 years 8 months ago
Integrated coverage and connectivity configuration in wireless sensor networks
An effective approach for energy conservation in wireless sensor networks is scheduling sleep intervals for extraneous nodes, while the remaining nodes stay active to provide cont...
Xiaorui Wang, Guoliang Xing, Yuanfang Zhang, Cheny...
PLDI
2010
ACM
15 years 8 months ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
15 years 8 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
RIDE
2002
IEEE
15 years 8 months ago
A Scheme for Integrating e-Services in Establishing Virtual Enterprises
An important aspect of Business to Business ECommerce is the agile Virtual Enterprise (VE). VEs are established when existing enterprises dynamically form temporary alliances, joi...
Alan Berfield, Panos K. Chrysanthis, Ioannis Tsama...
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