35 search results - page 6 / 7 » Dynamic configuration steering for a reconfigurable supersca... |
DAC
2002
ACM
14 years 7 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
TVLSI
2008
13 years 6 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
GECCO
2009
Springer
13 years 4 months ago
2009
Springer
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
CF
2007
ACM
13 years 10 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
EUROPAR
2005
Springer
13 years 12 months ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...