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VTS
1996
IEEE
126views Hardware» more  VTS 1996»
13 years 10 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DATE
2006
IEEE
99views Hardware» more  DATE 2006»
14 years 10 days ago
Multiple-fault diagnosis based on single-fault activation and single-output observation
In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multipl...
Yung-Chieh Lin, Kwang-Ting Cheng
DAC
1994
ACM
13 years 10 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
VTS
2000
IEEE
113views Hardware» more  VTS 2000»
13 years 10 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...
EVOW
1999
Springer
13 years 10 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...