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» Dynamic hardware software partitioning: a first approach
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FCCM
2007
IEEE
107views VLSI» more  FCCM 2007»
15 years 6 months ago
Optimizing Logarithmic Arithmetic on FPGAs
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
Haohuan Fu, Oskar Mencer, Wayne Luk
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 4 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
DAGSTUHL
2004
15 years 1 months ago
The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor
The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and c...
Xin Li, Reinhard von Hanxleden
MAM
2006
78views more  MAM 2006»
14 years 11 months ago
Operating system power minimization through run-time processor resource adaptation
The increasingly constrained power budget of today's microprocessor has resulted in a situation where power savings of all components in a system have to be taken into consid...
Tao Li, Lizy Kurian John
COMPSAC
2009
IEEE
15 years 4 months ago
Tool Support for Design Pattern Recognition at Model Level
Given the rapid rise of model-driven software development methodologies, it is highly desirable that tools be developed to support the use of design patterns in this context. This...
Hong Zhu, Ian Bayley, Lijun Shan, Richard Amphlett