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» Dynamic hardware software partitioning: a first approach
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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 1 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
BMCBI
2007
233views more  BMCBI 2007»
14 years 9 months ago
160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
Isaac T. S. Li, Warren Shum, Kevin Truong
SP
2008
IEEE
138views Security Privacy» more  SP 2008»
14 years 9 months ago
A performance tuning methodology with compiler support
We have developed an environment, based upon robust, existing, open source software, for tuning applications written using MPI, OpenMP or both. The goal of this effort, which inte...
Oscar Hernandez, Barbara M. Chapman, Haoqiang Jin
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
SIGMETRICS
2002
ACM
14 years 9 months ago
Full-system timing-first simulation
Computer system designers often evaluate future design alternatives with detailed simulators that strive for functional fidelity (to execute relevant workloads) and performance fi...
Carl J. Mauer, Mark D. Hill, David A. Wood