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» Dynamic hardware software partitioning: a first approach
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ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 5 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
MICRO
2006
IEEE
94views Hardware» more  MICRO 2006»
14 years 11 months ago
A Sampling Method Focusing on Practicality
In the past few years, several research works have demonstrated that sampling can drastically speed up architecture simulation, and several of these sampling techniques are already...
Daniel Gracia Pérez, Hugues Berry, Olivier ...
CODES
2009
IEEE
15 years 3 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
ICSE
1998
IEEE-ACM
15 years 4 months ago
Non-Intrusive Object Introspection in C++: Architecture and Application
We describe the design and implementation of system architecture to support object introspection in C++. In this system, information is collected by parsing class declarations, an...
Tyng-Ruey Chuang, Y. S. Kuo, Chien-Min Wang
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
15 years 3 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili