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HPCA
2012
IEEE
13 years 5 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
DAC
2007
ACM
15 years 10 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
DAC
2001
ACM
15 years 10 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
SIGSOFT
2003
ACM
15 years 10 months ago
Consistency techniques for interprocedural test data generation
This paper presents a novel approach for automated test data generation of imperative programs containing integer, boolean and/or float variables. It extends our previous work to ...
Nguyen Tran Sy, Yves Deville
SIGSOFT
2003
ACM
15 years 10 months ago
Protecting C programs from attacks via invalid pointer dereferences
Writes via unchecked pointer dereferences rank high among vulnerabilities most often exploited by malicious code. The most common attacks use an unchecked string copy to cause a b...
Suan Hsi Yong, Susan Horwitz
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