65 search results - page 3 / 13 » Dynamic power-performance adaptation of parallel computation... |
IEEEPACT
2009
IEEE
13 years 4 months ago
2009
IEEE
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
ISCA
2007
IEEE
14 years 17 days ago
2007
IEEE
We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...
ISCA
2007
IEEE
14 years 17 days ago
2007
IEEE
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
ICS
2009
Tsinghua U.
14 years 1 months ago
2009
Tsinghua U.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
DSN
2011
IEEE
12 years 6 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...