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ERSA
2006
197views Hardware» more  ERSA 2006»
15 years 3 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
IPPS
1999
IEEE
15 years 6 months ago
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 6 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
116
Voted
LCN
2002
IEEE
15 years 6 months ago
Design and Analysis of a Dynamically Reconfigurable Network Processor
The combination of high-performance processing power and flexibility found in network processors (NPs) has made them a good solution for today’s packet processing needs. Similar...
Ian A. Troxel, Alan D. George, Sarp Oral