Sciweavers

541 search results - page 22 / 109
» Dynamically Reconfigurable Architecture for Image Processor ...
Sort
View
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 8 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
104
Voted
FCCM
2004
IEEE
136views VLSI» more  FCCM 2004»
15 years 5 months ago
The MOLEN Processor Prototype
We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyp...
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassi...
136
Voted
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 7 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
GCC
2004
Springer
15 years 7 months ago
Distributed Object Group Framework with Dynamic Reconfigurability of Distributed Services
Abstract. In this paper, we constructed the Distributed Object Group Framework(DOGF) which is a reconfigurable architecture supporting dynamically adaptation of distributed service...
Chang-Sun Shin, Young-Jee Chung, Su-Chong Joo
126
Voted
VLSISP
2008
129views more  VLSISP 2008»
15 years 1 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...