541 search results - page 23 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
129
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IWSOC
2003
IEEE
15 years 7 months ago
2003
IEEE
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
108
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ERSA
2006
15 years 3 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
122
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CODES
2002
IEEE
15 years 6 months ago
2002
IEEE
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
131
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Publication
_2011.jpg "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision")
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
112
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...