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DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 8 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
CGO
2006
IEEE
15 years 8 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
DATE
2007
IEEE
110views Hardware» more  DATE 2007»
15 years 8 months ago
Reconfigurable system-on-chip data processing units for space imaging instruments
Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. To overcome the limitations of trad...
Björn Fiethe, Harald Michalik, C. Dierker, Bj...
JRTIP
2008
300views more  JRTIP 2008»
15 years 1 months ago
Real-time human action recognition on an embedded, reconfigurable video processing architecture
Abstract In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a realtime, emb...
Hongying Meng, Michael Freeman, Nick Pears, Chris ...
JRTIP
2008
249views more  JRTIP 2008»
15 years 1 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...