541 search results - page 32 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
128
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ICCD
2007
IEEE
15 years 5 months ago
2007
IEEE
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
168
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CC
2008
Springer
15 years 3 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
125
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IPPS
2005
IEEE
15 years 7 months ago
2005
IEEE
We propose in this paper an original design space exploration method for reconfigurable architectures adapted to fine and coarse grain resources. The exploration flow deals with c...
116
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ARC
2007
Springer
15 years 6 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
109
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FCCM
2004
IEEE
15 years 5 months ago
2004
IEEE
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...