541 search results - page 35 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
156
click to vote
ICPPW
2006
IEEE
15 years 10 months ago
2006
IEEE
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
137
click to vote
ISPA
2007
Springer
15 years 10 months ago
2007
Springer
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
174
click to vote
VLSID
2004
IEEE
16 years 4 months ago
2004
IEEE
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
111
click to vote
FPL
2007
Springer
15 years 10 months ago
2007
Springer
A biological organism’s ability to sense and adapt to its environment is essential to its survival. Likewise, environmentally aware computing systems avail themselves to a longe...
144
click to vote
DATE
2010
IEEE
15 years 9 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...