541 search results - page 38 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
147
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ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
128
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ICCD
1992
IEEE
15 years 8 months ago
1992
IEEE
This paper presents a data- ow computer, constituted of a large array of data- ow processors and programmed using a functional language, and its application to realtime image proc...
136
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ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
172
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CAMP
2005
IEEE
15 years 6 months ago
2005
IEEE
— We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embed...
136
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MOBICOM
1997
ACM
15 years 7 months ago
1997
ACM
Hot swapping technology combined with pervasive heterogeneous networks empowers mobile laptop users to select the best network device for their current environment. Unfortunately,...