541 search results - page 39 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
123
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ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA ext...
128
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JIRS
2007
15 years 4 months ago
2007
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
129
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
144
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IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
HeteroSort load balances and sorts within static or dynamic networks. Upon failure of a node or path, HeteroSort uses a genetic algorithm to minimize the distribution path by optim...
ISCA
2003
IEEE
15 years 9 months ago
2003
IEEE
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...