541 search results - page 50 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
122
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SAMOS
2009
Springer
15 years 10 months ago
2009
Springer
Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software s...
128
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VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
139
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DAC
2001
ACM
16 years 5 months ago
2001
ACM
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
165
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SAMOS
2010
Springer
15 years 2 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
133
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MIDDLEWARE
2004
Springer
15 years 9 months ago
2004
Springer
Middleware helps to manage the complexity and heterogeneity inherent in distributed systems. Traditional middleware has a monolithic architecture, which makes it difficult to adap...