Sciweavers

541 search results - page 57 / 109
» Dynamically Reconfigurable Architecture for Image Processor ...
Sort
View
HPDC
2009
IEEE
15 years 8 months ago
Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
Björn Saballus, Thomas Fuhrmann
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
15 years 8 months ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...
IISWC
2008
IEEE
15 years 8 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
15 years 4 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
15 years 7 months ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...