541 search results - page 73 / 109 » Dynamically Reconfigurable Architecture for Image Processor ... |
114
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WCAE
2006
ACM
15 years 7 months ago
2006
ACM
At Northeastern University we are building a number of courses upon a common embedded systems platform. The goal is to reduce the learning curve associated with new architectures ...
119
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HPCA
2000
IEEE
15 years 6 months ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
128
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CF
2010
ACM
15 years 5 months ago
2010
ACM
: The SpiNNaker machine is a massively parallel computing system, consisting of 1,000,000 cores. From one perspective, it has a place in Flynns' taxonomy: it is a straightforw...
120
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MICRO
2010
IEEE
14 years 11 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
123
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ICCD
2003
IEEE
15 years 10 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...