Sciweavers

541 search results - page 92 / 109
» Dynamically Reconfigurable Architecture for Image Processor ...
Sort
View
ASPLOS
2010
ACM
15 years 7 months ago
Modeling GPU-CPU workloads and systems
Heterogeneous systems, systems with multiple processors tailored for specialized tasks, are challenging programming environments. While it may be possible for domain experts to op...
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanch...
JPDC
2010
106views more  JPDC 2010»
15 years 8 days ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
15 years 6 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
ASPLOS
2006
ACM
15 years 7 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
ERSA
2003
301views Hardware» more  ERSA 2003»
15 years 3 months ago
A Configurable Hardware Scheduler for Real-Time Systems
Many real-time applications require a high-resolution time tick in order to work properly. However, supporting a high-resolution time tick imposes a very high overhead on the syst...
Pramote Kuacharoen, Mohamed Shalan, Vincent John M...