Sciweavers

541 search results - page 98 / 109
» Dynamically Reconfigurable Architecture for Image Processor ...
Sort
View
HPCA
2002
IEEE
16 years 2 months ago
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although c...
Peter Jamieson, Angelos Bilas
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
15 years 8 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
DAGSTUHL
2011
14 years 1 months ago
Interactive Isocontouring of High-Order Surfaces
Scientists and engineers are making increasingly use of hp-adaptive discretization methods to compute simulations. While techniques for isocontouring the high-order data generated...
Christian Azambuja Pagot, Joachim E. Vollrath, Fil...
HOTOS
1997
IEEE
15 years 6 months ago
Run-Time Code Generation as a Central System Service
We are building an operating system in which an integral run-time code generator constantly strives to improve the quality of already executing code. Our system is based on a plat...
Michael Franz
WMPI
2004
ACM
15 years 7 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström