130 search results - page 11 / 26 » Dynamically Scheduling VLIW Instructions |
73
Voted
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
86
Voted
PPOPP
1990
ACM
15 years 1 months ago
1990
ACM
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
95
Voted
DSD
2002
IEEE
15 years 2 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
93
Voted
MICRO
1991
IEEE
15 years 1 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...