130 search results - page 8 / 26 » Dynamically Scheduling VLIW Instructions |
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
IEEEPACT
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...
97
Voted
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
76
Voted
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...