Sciweavers

130 search results - page 9 / 26
» Dynamically Scheduling VLIW Instructions
Sort
View
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
15 years 2 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
CODES
2009
IEEE
15 years 1 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...
IEEEPACT
2002
IEEE
15 years 2 months ago
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning
This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters ...
Alex Aletà, Josep M. Codina, F. Jesú...
MICRO
2006
IEEE
107views Hardware» more  MICRO 2006»
14 years 9 months ago
Dataflow Predication
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
Aaron Smith, Ramadass Nagarajan, Karthikeyan Sanka...
83
Voted
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
15 years 2 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten