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IPPS
2006
IEEE
14 years 7 days ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 11 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ISPASS
2008
IEEE
14 years 19 days ago
Program Phase Detection based on Critical Basic Block Transitions
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
Paruj Ratanaworabhan, Martin Burtscher
HPCA
2009
IEEE
14 years 6 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
13 years 11 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...