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» E-Process Design and Assurance Using Model Checking
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59
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DAC
2007
ACM
15 years 2 months ago
Design for Verification in System-level Models and RTL
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
Anmol Mathur, Venkat Krishnaswamy
77
Voted
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
15 years 3 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
RTS
2006
176views more  RTS 2006»
14 years 10 months ago
Verifying distributed real-time properties of embedded systems via graph transformations and model checking
Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. C...
Gabor Madl, Sherif Abdelwahed, Douglas C. Schmidt
UML
2000
Springer
15 years 1 months ago
Using UML Collaboration Diagrams for Static Checking and Test Generation
Software testing can only be formalized and quanti ed when a solid basis for test generation can be de ned. Tests are commonly generated from program source code, graphical models ...
Aynur Abdurazik, A. Jefferson Offutt
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
15 years 4 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...