Sciweavers

597 search results - page 34 / 120
» E-Process Design and Assurance Using Model Checking
Sort
View
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
15 years 4 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
CAISE
2010
Springer
14 years 11 months ago
Design and Verification of Instantiable Compliance Rule Graphs in Process-Aware Information Systems
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
Linh Thao Ly, Stefanie Rinderle-Ma, Peter Dadam
92
Voted
ICST
2009
IEEE
15 years 4 months ago
Using JML Runtime Assertion Checking to Automate Metamorphic Testing in Applications without Test Oracles
It is challenging to test applications and functions for which the correct output for arbitrary input cannot be known in advance, e.g. some computational science or machine learni...
Christian Murphy, Kuang Shen, Gail E. Kaiser
70
Voted
CSFW
2006
IEEE
15 years 4 months ago
Decentralized Robustness
Robustness links confidentiality and integrity properties of a computing system and has been identified as a useful property for characterizing and enforcing security. Previous ...
Stephen Chong, Andrew C. Myers
107
Voted
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 5 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...