597 search results - page 47 / 120 » E-Process Design and Assurance Using Model Checking |
134
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ICCAD
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
136
Voted
WETICE
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper presents joint work by the California Institute of Technology’s Jet Propulsion Laboratory and the University of California at Davis (UC Davis) sponsored by the Nation...
118
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SPIN
2010
Springer
15 years 26 days ago
2010
Springer
This paper addresses the problem of verifying programs for the relaxed memory models implemented in modern processors. Specifically, it considers the TSO (Total Store Order) relax...
122
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FDL
2011
IEEE
14 years 2 months ago
2011
IEEE
—For the description of reactive systems, there is a large number of languages and formalisms, and depending on a particular application or design phase, one of them may be bette...
119
Voted
ECBS
2006
IEEE
15 years 8 months ago
2006
IEEE
The evolution of a design pattern typically involves the addition or removal of a group of modeling elements, such as classes, attributes, operations, and relationships. However, ...