597 search results - page 82 / 120 » E-Process Design and Assurance Using Model Checking |
156
Voted
DAC
2004
ACM
16 years 3 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
118
Voted
BCS
2008
15 years 3 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
97
Voted
ARTS
1997
Springer
15 years 6 months ago
1997
Springer
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
113
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ECLIPSE
2007
ACM
15 years 6 months ago
2007
ACM
In this paper we detail the design and implementation of an Eclipse plug-in that supports construction, analysis and elaboration of Modal Transition Systems. The plug-in supports ...
100
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QEST
2006
IEEE
15 years 8 months ago
2006
IEEE
This talk will provide an overview of work that I have done with Hana Chockler, Orna Kupferman, and Judea Pearl [1, 2, 10, 9] on defining notions such as causality, explanation, ...