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» E-Process Design and Assurance Using Model Checking
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125
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FOSSACS
2001
Springer
15 years 2 months ago
On Regular Message Sequence Chart Languages and Relationships to Mazurkiewicz Trace Theory
Hierarchical Message Sequence Charts are a well-established formalism to specify telecommunication protocols. In this model, numerous undecidability results were obtained recently ...
Rémi Morin
106
Voted
FMICS
2007
Springer
15 years 4 months ago
An Approach to Formalization and Analysis of Message Passing Libraries
Message passing using libraries implementing the Message Passing Interface (MPI) standard is the dominant communication mechanism in high performance computing (HPC) applications. ...
Robert Palmer, Michael Delisi, Ganesh Gopalakrishn...
FROCOS
2005
Springer
15 years 3 months ago
Sociable Interfaces
Interface formalisms are able to model both the input requirements and the output behavior of system components; they support both bottom-up component-based design, and top-down de...
Luca de Alfaro, Leandro Dias da Silva, Marco Faell...
116
Voted
ICFP
2010
ACM
14 years 11 months ago
VeriML: typed computation of logical terms inside a language with effects
Modern proof assistants such as Coq and Isabelle provide high degrees of expressiveness and assurance because they support formal reasoning in higher-order logic and supply explic...
Antonis Stampoulis, Zhong Shao
82
Voted
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
15 years 10 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng