Improvements in the software development process depend on our ability to collect and analyze data drawn from various phases of the development life cycle. Our design metrics rese...
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
This paper focuses on the development of a conceptual framework for integrating fault injection mechanisms into the RDD-100 tool2 to support the dependability analysis of computer...
We present a framework for designing end-to-end congestion control schemes in a network where each user may have a different utility function and may experience non-congestion-re...
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...