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RTAS
2007
IEEE
15 years 5 months ago
Optimizing the FPGA Implementation of HRT Systems
The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area...
Marco Di Natale, Enrico Bini
SIGSOFT
2004
ACM
15 years 12 months ago
Implementing protocols via declarative event patterns
This paper introduces declarative event patterns (DEPs) as a means to implement protocols while improving their traceability, comprehensibility, and maintainability. DEPs are desc...
Robert J. Walker, Kevin Viggers
ICCD
2006
IEEE
107views Hardware» more  ICCD 2006»
15 years 8 months ago
Design and Implementation of the TRIPS Primary Memory System
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
Simha Sethumadhavan, Robert G. McDonald, Rajagopal...
RECONFIG
2009
IEEE
118views VLSI» more  RECONFIG 2009»
15 years 6 months ago
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations
Abstract. Protecting an implementation against Side Channel Analysis for Reverse Engineering (SCARE) attacks is a great challenge and we address this challenge by presenting a fir...
Julien Bringer, Hervé Chabanne, Jean-Luc Da...
ICRA
2009
IEEE
204views Robotics» more  ICRA 2009»
15 years 5 months ago
A high-speed multi-GPU implementation of bottom-up attention using CUDA
— In this paper a novel implementation of the saliency map model on a multi-GPU platform using CUDA technology is presented. The saliency map model is a wellknown computational m...
Tingting Xu, Thomas Pototschnig, Kolja Kühnle...