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ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
15 years 5 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek
IJCNN
2006
IEEE
15 years 5 months ago
Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model
— This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI1 model of a spiking neural network. The artificial...
Johannes Schemmel, Andreas Grübl, Karlheinz M...
ISCAS
2006
IEEE
163views Hardware» more  ISCAS 2006»
15 years 5 months ago
ASIC hardware implementation of the IDEA NXT encryption algorithm
— Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a nov...
Marco Macchetti, Wenyu Chen
FCCM
1999
IEEE
143views VLSI» more  FCCM 1999»
15 years 3 months ago
Implementation and Evaluation of a Prototype Reconfigurable Router
The evolution of computer networking technology will likely require hardware that is flexible enough to adapt to changing standards while maintaining the highest possible performa...
Jason R. Hess, David C. Lee, Scott J. Harper, Mark...
ICLP
2010
Springer
15 years 3 months ago
Implementation Alternatives for Bottom-Up Evaluation
Abstract. Bottom-up evaluation is a central part of query evaluation / program execution in deductive databases. It is used after a source code optimization like magic sets or SLDm...
Stefan Brass