150 search results - page 17 / 30 » ECO timing optimization using spare cells |
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
VMV
2001
14 years 11 months ago
2001
Efficient isosurface extraction from large volume data sets requires special algorithms and data structures. Such algorithms typically either use a hierarchical spatial subdivisio...
ICCAD
2004
IEEE
15 years 7 months ago
2004
IEEE
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
BIOINFORMATICS
2011
14 years 5 months ago
2011
Motivation: Analysis and intervention in the dynamics of gene regulatory networks is at the heart of emerging efforts in the development of modern treatment of numerous ailments i...
STOC
2002
ACM
15 years 10 months ago
2002
ACM
Given a set S of n points in IRd , a (t, )-approximate Voronoi diagram (AVD) is a partition of space into constant complexity cells, where each cell c is associated with t represe...