150 search results - page 19 / 30 » ECO timing optimization using spare cells |
ISPD
2006
ACM
15 years 4 months ago
2006
ACM
Linear programming (LP) based methods are attractive for solving the placement problem because of their ability to model Half-Perimeter Wirelength (HPWL) and timing. However, it h...
ECAI
2010
Springer
14 years 10 months ago
2010
Springer
AI Planning is concerned with the selection of actions towards achieving a goal. Research on cellular automata (CA) is concerned with the question how global behaviours arise from ...
DAC
2000
ACM
15 years 11 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
VTS
2007
IEEE
15 years 4 months ago
2007
IEEE
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
EUROGP
2000
Springer
15 years 1 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...