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2011
14 years 1 months ago
Cost Effective Storage using Extent Based Dynamic Tiering
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
Jorge Guerra, Himabindu Pucha, Joseph S. Glider, W...
DAC
2002
ACM
15 years 10 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
14 years 9 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
AUTOMATICA
2008
89views more  AUTOMATICA 2008»
14 years 9 months ago
Dynamic buffer management using optimal control of hybrid systems
This paper studies a general dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multi...
Wei Zhang, Jianghai Hu
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
15 years 6 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...