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» ESL solutions for low power design
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ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 3 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
CODES
2001
IEEE
15 years 1 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 1 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
15 years 1 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
PIMRC
2008
IEEE
15 years 4 months ago
Radio-Triggered Wake-ups with Addressing Capabilities for extremely low power sensor network applications
Sensor network applications are generally characterized by long idle durations and intermittent communication patterns. The traffic loads are typically so low that overall idle d...
Junaid Ansari, Dmitry Pankin, Petri Mähö...