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DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
QI
2009
Springer
123views Physics» more  QI 2009»
15 years 4 months ago
Hilbert Space Models Commodity Exchanges
Abstract. It is argued that the vector space measures used to measure closeness of market prices to predictors for market prices are invalid because of the observed metric of commo...
Paul Cockshott
CODES
2008
IEEE
15 years 4 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
ISPASS
2008
IEEE
15 years 4 months ago
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
Transactional memory (TM) is a scalable and concurrent way to build atomic sections. One aspect of TM that remains unclear is how side-effecting operations – that is, those whic...
Lee Baugh, Craig B. Zilles
ISQED
2007
IEEE
141views Hardware» more  ISQED 2007»
15 years 4 months ago
OPC-Friendly Bus Driven Floorplanning
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. W...