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IPPS
2006
IEEE
15 years 3 months ago
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
Kostas Siozios, Konstantinos Tatas, Dimitrios Soud...
ICPPW
2002
IEEE
15 years 2 months ago
A Study of Dynamic Routing and Wavelength Assignment with Imprecise Network State Information
In large networks, maintaining precise global network state information is almost impossible. Many factors, such as non-negligible propagation delay, infrequent state updates due ...
Jun Zhou, Xin Yuan
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
15 years 1 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
MASCOTS
2004
14 years 11 months ago
Size-Based Scheduling Policies with Inaccurate Scheduling Information
Size-based scheduling policies such as SRPT have been studied since 1960s and have been applied in various arenas including packet networks and web server scheduling. SRPT has bee...
Dong Lu, Huanyuan Sheng, Peter A. Dinda
INFOCOM
2010
IEEE
14 years 8 months ago
Spatio-Temporal Fusion for Small-scale Primary Detection in Cognitive Radio Networks
Abstract—In cognitive radio networks (CRNs), detecting smallscale primary devices—such as wireless microphones (WMs)— is a challenging, but very important, problem that has n...
Alexander W. Min, Xinyu Zhang, Kang G. Shin