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DAC
2005
ACM
15 years 10 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
TVLSI
2008
176views more  TVLSI 2008»
14 years 9 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
15 years 2 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
DAC
2006
ACM
15 years 10 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
ICC
2007
IEEE
103views Communications» more  ICC 2007»
15 years 4 months ago
Advanced Channel Estimation for MIMO-OFDM in Realistic Channel Conditions
— An advanced decision-directed channel estimation scheme is proposed, which is suitable for employment in a wide range of multi-antenna multi-carrier systems as well as for comm...
Jos Akhtman, Lajos Hanzo