—In this work, we study the effects of finite buffers on the throughput and delay of line networks with erasure links. We identify the calculation of performance parameters such...
Badri N. Vellambi, Nima Torabkhani, Faramarz Fekri
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
Song Jin, Yinhe Han, Lei Zhang 0008, Huawei Li, Xi...
—Given limited resource and time before software release, development-site testing and debugging become more and more insufficient to ensure satisfactory software performance. As...
Shi Han, Yingnong Dang, Song Ge, Dongmei Zhang, Ta...
Abstract—The optimal transmit strategies of single-user multiantenna systems with respect to average capacity maximization are well understood. However, the performance measure d...
Eduard A. Jorswieck, Rami Mochaourab, Martin Mitte...