With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
Studies examining medial temporal lobe (MTL) involvement in memory formation typically assess memory performance after a single, short delay. Thus, the relationship between MTL en...
Valerie A. Carr, Indre V. Viskontas, Stephen A. En...
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
A common feature of congestion control protocols is the presence of information packets used to signal congestion. We address here the question of how frequently such protocols nee...
There exists a high demand for reliable, high capacity underwater acoustic networks to allow efficient data gathering and information exchange. This is evidenced by significant re...