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ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
15 years 6 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
INFOCOM
2012
IEEE
13 years 4 months ago
LBA: Lifetime balanced data aggregation in low duty cycle sensor networks
—This paper proposes LBA, a lifetime balanced data aggregation scheme for asynchronous and duty cycle sensor networks under an application-specific requirement of end-to-end dat...
Zi Li, Yang Peng, Daji Qiao, Wensheng Zhang
TCAD
2008
136views more  TCAD 2008»
15 years 1 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
CODES
2009
IEEE
15 years 5 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 5 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...