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HPCA
2009
IEEE
16 years 7 days ago
Voltage emergency prediction: Using signatures to reduce operating margins
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. H...
DAC
2006
ACM
16 years 20 days ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
MMNS
2001
151views Multimedia» more  MMNS 2001»
15 years 1 months ago
Analysis of Random Access Protocol under Bursty Traffic
Aloha-type random-access protocols have been employed as access control protocols in wireline and wireless, stationary and mobile, multiple-access communications networks. They are...
Jianbo Gao, Izhak Rubin
ISPASS
2006
IEEE
15 years 5 months ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 5 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...